2021 Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS)

Beyond and More than Moore devices characterisation/simulation and applications (I)

Session Chair: Pierpaolo Palestri (University of Udine, Italy)

› Modeling Low and High Field Uniform Transport in Monolayer MoS2 - alessandro pilotto, DPIA University of Udine 09:00-09:20 (20min)

› Synaptic transistors based on transparent oxide for neural image recognition - Q N Wang, AI University Research Centre (AI-URC), Xi'an Jiaotong-Liverpool University, Department of Electrical Engineering and Electronics, University of Liverpool, School of Advanced Technology, Xi'an Jiaotong-Liverpool University 09:40-10:00 (20min)

› Thermal Stability of Ferroelectricity in Hafnia-Zirconia-Alumina Buried Oxide Stacks - Vladimir Popov, A.V. Rzhanov Institute of Semiconductor Physics 10:00-10:20 (20min)

Coffee break

Engineering Trap-Rich layers for communication applications

Frederic Allibert

Advanced and Innovative SOI Architectures (II)

Session Co-Chairs: Pierpaolo Palestri (University of Udine, Italy), Bogdan Cretu (ENSICAEN, France)

› High performance silicon-based substrate using buried PN junctions towards RF applications - Maxime Moulin, CEA-Leti 11:20-11:40 (20min)

› New 10V to 1V level shifter based on new N/PMOS high voltage in FDSOI technology - Philippe Galy, STMicroelectronics [Grenoble] 11:40-12:00 (20min)

Lunch Break

If you cannot beat CMOS with TFETs, you join it with TFTs and sensors

Alexander Zaslavsky

Beyond and More than Moore devices characterisation/simulation and applications (II)

Session Chair: Alexander Zaslavsky (Brown University, USA)

› Improved inter-device variability in graphene liquid gate sensors by laser treatment - Jorge Avila, Nanoelectronics Research Group (CITIC-UGR), Department of Electronics, University of Granada, 18071, Granada, Spain - Jose Galdon, Nanoelectronics Research Group (CITIC-UGR), Department of Electronics, University of Granada, 18071, Granada, Spain - Francisco Gamiz, Nanoelectronics Research Group (CITIC-UGR), Department of Electronics, University of Granada, 18071, Granada, Spain 14:40-15:00 (20min)

› Numerical Device Modeling of High-Aspect Ratio FinFET based pH-Nanosensor - Rakshita Dhar, University of Glasgow 15:00-15:20 (20min)

Coffee break

Advanced and Innovative SOI Architectures (III)

Session Chair: Frederic Allibert (SOITEC, France)

› A theoretical study of electron mobility distribution in FDSOI MOSFET - Nima Dehdashti Akhavan, The University of Western Australia 15:40-16:00 (20min)

› Performance of Stacked SOI Nanowires in a Wide Temperature Range - Jaime Rodrigues, Centro Universitário FEI - Sylvain Barraud, Laboratoire d'Electronique et des Technologies de l'Information (CEA-LETI) 16:00-16:20 (20min)

Modelling and Characterisation

Session Chair: Frederic Allibert (SOITEC, France)

› Characterization and Lambert-W Function based modeling of FDSOI five-gate qubit MOS devices down to cryogenic temperatures - Edoardo Catapano, Commissariat à l\'énergie atomique et aux énergies alternatives - Laboratoire dÉlectronique et de Technologie de lÍnformation, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d\'Hyperfréquences et Caractérisation 16:20-16:40 (20min)

› High Temperature Influence on the Trade-off between gm/ID and fT of nanosheet NMOS Transistors with Different Metal Gate Stack - Vanessa Silva, University of São Paulo 16:40-17:00 (20min)

› Comprehensive Kubo-Greenwood modelling of FDSOI MOS devices down to deep cryogenic temperatures - Francesco Serra di Santa Maria, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d\'Hyperfréquences et Caractérisation 17:00-17:20 (20min)

city center Caen

Gala Dinner

Program